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Ravi Achanta
Also published under:R. Achanta
Affiliation
GlobalFoundries, NY, USA
Topic
Hot Electrons,Amorphous Layer,Bias Conditions,CMOS Technology,Capacity Density,Continuous Wave,Device Structure,Dielectric Process,Dielectric Relaxation,Differential Pair,Drain Current,Gate Length,High Performance,High Voltage,Hot Carrier Effect,Hot Injection,Low-noise Amplifier,Maximum Voltage,Mm-wave Power Amplifier,Noise Figure,OFF State,Output Power,Paper Reports,Power Amplifier,Space Applications,Tin Electrodes,Top Plate,Transconductance,Voltage Support,Dielectric Breakdown,Low Voltage,Weibull Distribution,Activation Energy,Gate Dielectric,Low Field,Lower Percentile,Voltage Stress,Acceleration Voltage,Cluster Model,Cu Interconnects,Local Field,Time-dependent Model,Acceleration Model,Charge Transport,Copper Accumulation,Copper Ions,Defect Density,Electromigration,Experimental Data Points,Exponential Term,
Biography
Ravi Achanta is a Reliability Engineer with the Microelectronics Division, IBM, Hopewell Junction, NY, USA. He is involved in the reliability evaluation and certification of low-$k$ and high-$k$ time-dependent-dielectric-breakdown material processes. His research interests include microelectronics materials reliability and statistics and the study of transport processes involved in understanding materials behavior.